The advancement of the semiconductor technology has raised the requirements of processing speed and functionality for chips, which induces a concern of how to effectively dissipate heat produced during operation of the chips so as to assure the reliability of semiconductor devices where the chips are incorporated. For example, a ball grid array (BGA) semiconductor package is usually used with devices having a large number of input/output (I/O) connections for highly integrated chips, such as 2D or 3D graphic chip, chip set, central processing unit (CPU), and memory, etc. If the heat dissipation problem cannot be properly solved, the performances of these devices would be adversely affected. Therefore, a solution to the heat dissipation problem has been proposed by mounting a heat sink in a semiconductor package.
In the conventional BGA semiconductor package, a typical heat dissipating path is to transmit heat from the chip through a silver paste, a substrate and thermal balls under the substrate, or through an encapsulant that encapsulates the chip, to outside of the semiconductor package. This heat dissipating path is relatively lengthy and does not provide a sufficient heat dissipating efficiency. In order to solve the heat dissipation problem, generally an exposed heat sink made of copper or aluminum is mounted on the BGA semiconductor package. As shown in FIG. 1, the semiconductor package with the exposed heat sink comprises: a substrate 11; a chip 12 attached to the substrate 11; a heat sink 13 mounted on the substrate 11; and an encapsulant 14 for encapsulating a portion of the substrate 11, the chip 12 and the heat sink 13, wherein the heat sink 13 comprises a bent support portion 131 for supporting the entire heat sink 13 and forming a space where the chip 12 is received. By this arrangement, heat produced by the chip 12 can be directly dissipated to the atmosphere via an exposed surface 130 of the heat sink 13 that has good thermal conductivity. Alternatively, a heat pipe or fan (not shown) can be externally mounted on the exposed surface 130 of the heat sink 13, such that the heat from the chip 12 can be more effectively dissipated out of the semiconductor package via the heat sink 13 and the heat pipe or fan, and the heat dissipating efficiency of the semiconductor package can be further improved.
The foregoing semiconductor package can desirably improve the heat dissipating efficiency thereof, however, it still has a drawback during a molding process of forming the encapsulant 14 in order to expose the surface 130 of the heat sink 13. As shown in FIG. 2, during the molding process, the surface 130 of the heat sink 13 to be exposed abuts against an inner surface 150 of an upper mold 15 of an encapsulating mold, such that the encapsulant 14 injected into a mold cavity of the upper mold 15 would not cover the surface 130 of the heat sink 13, and the surface 130 of the heat sink 13 can be exposed when the encapsulant 14 is cured. However, the surface 130 of the heat sink 13 may not be perfectly planar due to undesirable rolled portions being possibly formed at edges of the heat sink 13 fabricated by a stamping technique. This makes the surface 130 of the heat sink 13 not able to tightly abut against the inner surface 150 of the upper mold 15 during molding; further as the support portion 131 of the heat sink 13 is not effective to reduce a flowing speed of the encapsulant 14 and control the movement of the encapsulant 14, the encapsulant 14 may flash to gaps between the surface 130 of the heat sink 13 and the inner surface 150 of the upper mold 15, thereby causing flashes f of the encapsulant 14 on the exposed surface 130 of the heat sink 13 as shown in FIG. 3. This not only impairs the appearance of the packaged product but also reduces the heat dissipating area and the heat dissipating efficiency. If an additional deflash process is performed to remove the flashes f, the packaging cost would be increased and the fabricating processes would become complicated.
In light of the above flash problem, another heat sink structure has been proposed so as to reduce flashes of an encapsulant during molding. U.S. Pat. No. 6,249,433 has disclosed an exposed drop-in heat sink plastic ball grid array (EDHS-PBGA) semiconductor package for reducing flashes and improving the heat dissipating efficiency. As shown in FIG. 4A, this semiconductor package comprises a substrate 30; a chip 31 attached to the substrate 30 via an adhesive layer 34; a heat sink 32 mounted on the substrate 30; and an encapsulant 33 for encapsulating a portion of the substrate 30, the chip 31 and the heat sink 32. The heat sink 32 comprises a flat portion 325 having an exposed surface 321 and an inner surface 322, and a support portion 326 extended peripherally from the flat portion 325 and mounted on the substrate 30. The inner surface 322 of the flat portion 325 is spaced from bonding wires 36 and an active surface 310 of the chip 31 respectively by a predetermined distance. The exposed surface 321 of the flat portion 325 of the heat sink 32 is exposed from the encapsulant 33, such that heat produced by the chip 31 can be dissipated out of the semiconductor package via the exposed surface 321.
Further as shown in FIG. 4A, the exposed surface 321 of the flat portion 325 of the heat sink 32 is formed with a stepped structure 323 for preventing flashes. The stepped structure 323 comprises a first step surface 323a, a second step surface 323b, and a third step surface 323c, which have successively decreased elevations. During the molding process, when the encapsulant 33 is injected from an injection gate (not shown) and flows along the support portion 326 gradually to the third step surface 323c, due to a relatively smaller flow-accommodating space on the third step surface 323c, the encapsulant 33 would absorb heat from an encapsulating mold (not shown) and become more viscous to reduce its flowing speed. Then, when the encapsulant 33 enters the second step surface 323b, the flowing speed of the encapsulant 33 would be more reduced due to the even smaller flow-accommodating space on the second step surface 323b that is located in higher elevation than the third step surface 323c. Similarly, when the encapsulant 33 subsequently enters the topmost first step surface 323a where the flow-accommodating space becomes further smaller, the viscosity of the encapsulant 33 would be further increased to even reduce its flowing speed, thereby preventing the encapsulant 33 from flashing to the exposed surface 321 of the heat sink 32.
The above arrangement merely uses the gradually decreased flow-accommodating space caused by the specific stepped structure 323 of the heat sink 32 to reduce the flowing speed of the encapsulant 33. However, as the encapsulant 33 is made of resin and fillers, the stepped structure 323 can only prevent the relatively larger fillers from flashing to the exposed surface 321 of the heat sink 32 but is not effective to block the flow of resin that has high fluidity. Thus, the stepped structure 323 still fails to precisely control the movement of the encapsulant 33 and does not provide a satisfactory effect on blocking the flow of the encapsulant 33. As shown in FIGS. 4A and 4B, the transparent resin flashes f are formed on peripheral areas of the exposed surface 321 of the heat sink 32 as a result, and the resin flash problem is not properly solved. This similarly impairs the appearance of the packaged product and affects the heat dissipating efficiency. Moreover, if an additional deflash process is performed to remove the resin flashes f, the packaging cost would be increased and the fabricating processes would become complicated.
Therefore, the problem to be solved here is to provide a semiconductor package with an exposed heat sink, which can improve the heat dissipating efficiency and avoid the foregoing problems in the prior art.